Embodiments of the present invention relate generally to a non-volatile semiconductor memory circuit, and more particularly, to a non-volatile semiconductor memory circuit capable of improving a read margin.
Recently, phase change random access memory (PRAM) has been spotlighted as a non-volatile memory. The PRAM has been studied and developed because while the PRAM is non-volatile, the PRAM allows random data access. Accordingly, the PRAM is applied to various semiconductor systems and semiconductor memory devices.
A unit cell of the PRAM includes a cell transistor connected to a word line and a variable resistor, such as germanium antimony telluride (GST), which is connected to a bit line. The GST is a phase change material, such as a calcogenide (e.g. Ge2Sb2Te5) alloy having a thin thickness. That is, the GST is capable of having and changing between more than one material state. The GST has a high resistance in an amorphous state and a low resistance in a crystalline state. Using this aspect of the PRAM, data can be stored in a memory cell by using the two physical states of the GST based on the resistance difference in the GST.
FIG. 1 is a graph showing a voltage distribution of PRAM data.
Referring to FIG. 1, in the case of a single level cell, data can be classified into two types based on sensing voltage of a read operation, e.g., single reference voltage ‘VREF’. In detail, if data can be read at the reference voltage ‘VREF’, the data may be referred to as reset state data, that is, data of ‘1’. However, if the data can not be read at the reference voltage ‘VREF’, the data may be referred to as set state data, that is, data of ‘0’. In terms of resistance, if the GST has a high resistance, the data refers to data of ‘1’. However, if the GST has a low resistance, the data refers to data of ‘0’.
The phase of the GST in the PRAM is changed due to Joule heating caused by an application of an external electrical pulse. The phase of the GST in the PRAM can be controlled by using the electrical pulse through a process that will be referred to as a “set/reset” operation.
As described above, when the state of the data of the GST is controlled due to heat caused by a pulse current, if a heat change occurs, the resistivity of the GST is changed. Thus, resistance of each memory cell is distributed in a wide range, and a read margin between the crystalline state and the non-crystalline state may be reduced, causing deterioration of reliability of the PRAM cell.